A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS

Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used due to their low power consumption and area cost. However, testing SAR ADCs on an embedded chip is costly. This paper proposes a capacitance-ratio quantification design for the linearity test of differential top-plate sampling SAR ADCs. First, the pattern generator controls the switches connected to the bottom plate of capacitors to create a voltage difference proportional to a certain capacitance ratio on the top plates to be quantified. Then, the proposed mechanism quantifies the capacitance ratio via the auxiliary transistors connected to the input pair of the comparator in the SAR ADC. The capacitance ratios are recorded to construct the differential nonlinearity (DNL) and integral nonlinearity (INL) using the derived construction principles, which simplifies the implementation of the output response analyzer. Thus, the test time and area cost can be reduced with these two proposed mechanisms. For characterizing the DNL, the error between the results obtained using the proposed method and those obtained using conventional linear ramp histogram method is from 0.10 to 0.11 least significant bits (LSBs). For the INL, the estimation error is from 0.19 to 0.11 LSBs. Moreover, a test time reduction of about 76% is achieved at the expense of an 18.54% area overhead for the capacitance-ratio quantification mechanism. Copyright © 2014 John Wiley & Sons, Ltd.